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INTEGRATED CIRCUITS
DATA SHEET
UMA1020AM Low-voltage dual frequency synthesizer for radio telephones
Product specification Supersedes data of November 1994 File under Integrated Circuits, IC03 1995 Jul 06
Philips Semiconductors
Product specification
Low-voltage dual frequency synthesizer for radio telephones
FEATURES * Low current from 3 V supply * Fully programmable RF divider * 3-line serial interface bus * Second synthesizer to control first IF or offset loop frequency * Independent fully programmable reference dividers for each loop, driven from external crystal oscillator * Dual phase detector outputs to allow fast frequency switching * Dual power-down modes. APPLICATIONS * 1 to 1.7 GHz mobile telephones * Portable battery-powered radio equipment. GENERAL DESCRIPTION The UMA1020AM BICMOS device integrates prescalers, programmable dividers, and phase comparators to implement two phase-locked loops. The device is designed to operate from 3 NiCd cells, in pocket phones, with low current and nominal 5 V supplies. QUICK REFERENCE DATA SYMBOL VCC, VDD ICC + IDD PARAMETER supply voltage principal synthesizer supply current principal and auxiliary synthesizer supply current ICCPD, IDDPD fVCO fAI fXTAL fPPC fAPC Tamb current in power-down mode per supply principal input frequency auxiliary input frequency crystal reference input frequency principal phase comparator frequency auxiliary phase comparator frequency operating ambient temperature CONDITIONS VCC VDD auxiliary synthesizer in - power-down mode principal and auxiliary synthesizers ON - - 1000 20 3 - - -30 MIN. 2.7 -
UMA1020AM
The principal synthesizer operates at RF input frequencies up to 1.7 GHz the auxiliary synthesizer operates at 300 MHz. The auxiliary loop is intended for the first IF or to transmit offset loop-frequency settings. Each synthesizer has a fully programmable reference divider. All divider ratios are supplied via a 3-wire serial programming bus. Separate power and ground pins are provided to the analog and digital circuits. The ground leads should be externally short-circuited to prevent large currents flowing across the die and thus causing damage. Digital supplies VDD1 and VDD2 must also be at the same potential. VCC must be equal to or greater than VDD (i.e. VDD = 3 V and VCC = 5 V for wider tuning range). The principal synthesizer phase detector uses two charge pumps, one provides normal loop feedback, while the other is only active during fast mode to speed-up switching. The auxiliary loop has a separate phase detector. All charge pump currents (gain) are fixed by an external resistance at pin ISET (pin 14). Only passive loop filters are used; the charge-pumps function within a wide voltage compliance range to improve the overall system performance.
TYP. 9.4 12.1 12 1500 - - 200 200 -
MAX. 5.5 - - - 1700 300 40 - - +85
UNIT V mA mA A MHz MHz MHz kHz kHz C
ORDERING INFORMATION TYPE NUMBER UMA1020AM 1995 Jul 06 PACKAGE NAME SSOP20 DESCRIPTION plastic shrink small outline package; 20 leads; body width 4.4 mm 2 VERSION SOT266-1
Philips Semiconductors
Product specification
Low-voltage dual frequency synthesizer for radio telephones
BLOCK DIAGRAM
UMA1020AM
Fig.1 Block diagram.
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Philips Semiconductors
Product specification
Low-voltage dual frequency synthesizer for radio telephones
PINNING SYMBOL FAST CPPF CPP VDD1 VDD2 PRI DGND fXTAL POFF n.c. CLK DATA E ISET AUX AGND CPA VCC AOFF LOCK PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION control input to speed-up main synthesizer principal synthesizer speed-up charge-pump output principal synthesizer normal charge-pump output digital power supply 1 digital power supply 2 1.7 GHz principal synthesizer frequency input digital ground common crystal frequency input from TCXO principal synthesizer power-down input not connected programming bus clock input programming bus data input programming bus enable input (active LOW) regulator pin to set the charge-pump currents auxiliary synthesizer frequency input analog ground auxiliary synthesizer charge-pump output supply for charge-pump auxiliary synthesizer power-down input in-lock detect output (main PLL); test mode output
UMA1020AM
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION Principal synthesizer Programmable reference and main dividers drive the principal PLL phase detector. Two charge pumps produce phase error current pulses for integration in an external loop filter. A hardwired power-down input POFF (pin 9) ensures that the dividers and phase comparator circuits can be disabled.
The PRI input (pin 6) drives a preamplifier to provide the clock to the first divider stage. The preamplifier has a high input impedance, dominated by pin and pad capacitance. The circuit operates with signal levels from 100 mV to 500 mV (RMS), and at frequencies up to 1.7 GHz. The high frequency divider circuits use bipolar transistors, slower bits are CMOS. Divider ratios (512 to 131071) allow up to 2 MHz phase comparison frequency.
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Philips Semiconductors
Product specification
Low-voltage dual frequency synthesizer for radio telephones
The reference and main divider outputs are connected to a phase/frequency detector that controls two charge pumps. The two pumps have a common bias-setting current that is set by an external resistance. The ratio between currents in fast and normal operating modes can be programmed via the 3-wire serial bus. The low current pump remains active except in power-down. The high current pump is enabled via the control input FAST (pin 1). By appropriate connection to the loop filter, dual bandwidth loops are provided: short time constant during frequency switching (FAST mode) to speed-up channel changes and low bandwidth in the settled state (on-frequency) to reduce noise and breakthrough levels. The principal synthesizer speed-up charge pump (CPPF) is controlled by the FAST input in synchronization with phase detector operation in such a way that potential disturbances are minimized. The dead zone (caused by finite time taken to switch the current sources on or off) is cancelled by feedback from the normal pump output to the phase detector thereby improving linearity. An open drain transistor drives the output pin LOCK (pin 20). It is recommended that the pull-up resistor from this pin to VDD is chosen such that the value is high enough to keep the sink current in the LOW state below 400 A. The circuit can be programmed to output either the phase error in the principal or auxiliary phase detectors or the combination from both detectors (OR function). The resultant output will be a current pulse with the duration of the selected phase error. By appropriate external filtering and threshold comparison, an out-of-lock or an in-lock flag is generated. Auxiliary synthesizer The auxiliary synthesizer has a 14-bit main divider and an 11-bit reference divider. A separate power-down input AOFF (pin 19), disables currents in the auxiliary dividers, phase detector, and charge pump. The auxiliary input signal is amplified and fed to the main divider. The input buffer presents a high impedance, dominated by pin and pad capacitance. First divider stages use bipolar technology operating at input frequencies up to 300 MHz; the slower bits are CMOS. The auxiliary loop phase detector and charge pump use similar circuits to the main loop low-current phase comparator, including dead-zone compensation feedback. The auxiliary reference divider is clocked on the opposite edge of the principal reference divider to ensure that active edges arrive at the auxiliary and principal phase detectors at different times. This minimizes the potential for interference between the charge pumps of each loop. Serial programming bus
UMA1020AM
A simple 3-line unidirectional serial bus is used to program the circuit. The 3 lines are DATA, CLK and E (enable). The data sent to the device is loaded in bursts framed by E. Programming clock edges and their appropriate data bits are ignored until E goes active LOW. The programmed information is loaded into the addressed latch when E returns inactive HIGH. Only the last 21 bits serially clocked into the device are retained within the programming register. Additional leading bits are ignored, and no check is made on the number of clock pulses. The fully static CMOS design uses virtually no current when the bus is inactive. It can always capture new programmed data even during power-down of main and auxiliary loops. However when either principal synthesizer or auxiliary synthesizer or both are powered-on, the presence of a TCXO signal is required at pin 8 (fXTAL) for correct programming. Data format Data is entered with the most significant bit first. The leading bits make up the data field, while the trailing four bits are an address field. The UMA1020AM uses 5 of the 16 available addresses. The data format is shown in Table 1. The first entered bit is p1, the last bit is p21. The trailing address bits are decoded on the inactive edge of E. This produces an internal load pulse to store the data in one of the addressed latches. To ensure that the data is correctly loaded on first power-up, E should be held LOW and only taken HIGH after having programmed an appropriate register. To avoid erroneous divider ratios, the pulse is not allowed during data reads by the frequency dividers. This condition is guaranteed by respecting a minimum E pulse width after data transfer. The corresponding relationship between data fields and addresses is given in Table 2.
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Philips Semiconductors
Table 1
Format of programmed data
Low-voltage dual frequency synthesizer for radio telephones
LAST IN p21 ADD0 p20 ADD1 p19 ADD2
PROGRAMMING REGISTER BIT USAGE p18 ADD3 p17 DATA0 LSB p16 DATA1 ../.. ../.. DATA COEFFICIENT p2 DATA15
FIRST IN p1 DATA16 MSB
LATCH ADDRESS Table 2 FT p1 dt16 X PM16 X X X Notes X X X X X X X AM13 X X X AR10 X X p2 dt15 X p3 dt14 X p4 dt13 X p5 dt12 OLP OLA CR1 PR10 CR0 p6 p7 p8 Bit allocation (note 1)
REGISTER BIT ALLOCATION p9 p10 p11 p12 p13 p14 dt4 sPOFF sAOFF X dt3 X p15 dt2 X p16 p17 dt1 X dt0 0 X PM0 PR0 AM0 AR0 0 0 0 0 0 p18 p19 0 0 1 1 1 1 p20 0 0 0 0 1 1 DATA FIELD TEST BITS(2) X X PRINCIPAL MAIN DIVIDER COEFFICIENT PRINCIPAL REFERENCE DIVIDER COEFFICIENT AUXILIARY MAIN DIVIDER COEFFICIENT AUXILIARY REFERENCE DIVIDER COEFFICIENT ADDRESS
LT p21 0 1 0 1 0 1
1. FT = first, LT = last; sPOFF = software power-down for principal synthesizer (1 = OFF); sAOFF = software power-down for auxiliary synthesizer (1 = OFF). 2. The test register should not be programmed with any other value except all zeros for normal operation. Table 3 Out-of-lock select OLP 0 0 1 1 OLA 0 1 0 1 output disabled auxiliary phase error principal phase error both auxiliary and principal OUT-OF-LOCK ON PIN 20
UMA1020AM
Product specification
Philips Semiconductors
Product specification
Low-voltage dual frequency synthesizer for radio telephones
Table 4 CR1 0 0 1 1 Note V 14 1. ISET = ---------- ; common bias current for charge pumps. R ext Table 5 AOFF 1 1 1 0 0 0 Power-down modes POFF 1 0 0 1 0 0 FAST X 0 1 X 0 1 PRINCIPAL DIVIDERS OFF ON ON OFF ON ON AUXILIARY DIVIDERS OFF OFF OFF ON ON ON PUMP CPA OFF OFF OFF ON ON ON Fast and normal charge pumps current ratio (note 1) CR0 0 1 0 1 ICPA 4 x ISET 4 x ISET 4 x ISET 4 x ISET ICPP 4 x ISET 4 x ISET 2 x ISET 2 x ISET ICPPF 16 x ISET 32 x ISET 24 x ISET 32 x ISET
UMA1020AM
ICPPF : ICPP 4:1 8:1 12 : 1 16 : 1
PUMP CPP OFF ON ON OFF ON ON
PUMP CPPF OFF OFF ON OFF OFF ON
Power-down modes The action of the control inputs on the state of internal blocks is defined by Table 5. Note that in Table 5, POFF and AOFF can be either the software or hardware power-down signals. The dividers are ON when both hardware and software power-down signals are at logic 0.
When either synthesizer is reactivated after power-down the main and reference dividers of that synthesizer are synchronized to avoid the possibility of random phase errors on power-up.
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Philips Semiconductors
Product specification
Low-voltage dual frequency synthesizer for radio telephones
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VCC VCC-DD Vn V2, 3, 17 VGND Ptot Tstg Tamb Tj HANDLING digital supply voltage analog supply voltage difference in voltage between VCC and VDD voltage at pins 1, 6, 8 to 15, 19 and 20 voltage at pins 2, 3 and 17 difference in voltage between AGND and DGND (these pins should be connected together) total power dissipation storage temperature operating ambient temperature maximum junction temperature PARAMETER MIN. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 - -55 -30 -
UMA1020AM
MAX. +5.5 +5.5 +5.5 VDD + 0.3 VCC + 0.3 +0.3 150 +125 +85 95 V V V V V V
UNIT
mW C C C
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 120 UNIT K/W
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Philips Semiconductors
Product specification
Low-voltage dual frequency synthesizer for radio telephones
CHARACTERISTICS VDD1 = VDD2 = 2.7 to 5.5 V; VCC = 2.7 to 5.5 V; Tamb = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - - 9 2.7 0.4 12 TYP.
UMA1020AM
MAX.
UNIT
Supply; pins 4, 5 and 18 VDD VCC IDD digital supply voltage analog supply voltage principal synthesizer digital supply current auxiliary synthesizer digital supply current ICC charge pumps supply current VDD1 = VDD2 VCC VDD VDD = 5.5 V VDD = 5.5 V VCC = 5.5 V; Rext =12 k logic levels 0 or VDD 2.7 2.7 - - - - 5.5 5.5 11 4.0 1.0 50 V V mA mA mA A
ICCPD, IDDPD current in power-down mode per supply RF principal main divider input; pin 6 fVCO V6(rms) ZI CI Rpm fPPCmax fPPCmin RF input frequency AC-coupled input signal level (RMS value) input impedance (real part) typical pin input capacitance principal main divider ratio maximum principal phase comparator frequency minimum principal phase comparator frequency
1000 Rs = 50 fVCO = 1.7 GHz indicative, not tested 100 - - 512 - -
1500 - 300 2 - 2000 10
1700 500 - - 131071 - -
MHz mV pF kHz kHz
Auxiliary main divider input; pin 15 fAI V15(rms) input frequency AC-coupled input signal level (RMS value) Rs = 50 ; 2.7 V < VDD < 3.5 V Rs = 50 ; 3.5 V < VDD < 5.5 V ZI CI Ram fAPCmax fAPCmin input impedance (real part) typical pin input capacitance auxiliary main divider ratio maximum auxiliary loop comparison frequency minimum auxiliary loop comparison frequency fAI = 100 MHz indicative, not tested 20 50 100 - - 64 - - - - - 1 2 - 2000 10 300 500 500 - - 16383 - - kHz kHz MHz mV mV k pF
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Philips Semiconductors
Product specification
Low-voltage dual frequency synthesizer for radio telephones
SYMBOL PARAMETER CONDITIONS MIN. - - - 2 2 - - - 1.15 - 5 1 - - - - 2 - TYP.
UMA1020AM
MAX.
UNIT
Crystal reference dividers input; pin 8 fXTAL V8(rms) ZI CI Rpr Rar Rext V14 IOcp Imatch ILcp Vcp VIH VIL Ibias CI VOL crystal reference input frequency sinusoidal input signal level (RMS value) input impedance (real part) typical pin input capacitance principal reference divider ratio auxiliary reference divider ratio 3 5 MHz < fXTAL < 40 MHz 50 3 MHz < fXTAL < 40 MHz 100 fXTAL = 30 MHz indicative, not tested - - 8 8 40 500 500 - - 2047 2047 MHz mV mV k pF
Charge pump current setting resistor input; pin 14 external resistor from pin 14 to ground regulated voltage at pin 14 Rext = 12 k 12 - -25 Vcp in range Vcp = 12VCC - -5 0.4 60 - +25 - +5 k V
Charge pump outputs; pins 17, 3 and 2; Rext = 12 k charge pump output current error sink-to-source current matching charge pump off leakage current charge pump voltage compliance % % nA
VCC - 0.4 V VDD + 0.3 V 0.3VDD +5 - V A pF
Interface logic input signal levels; pins 13, 12, 11 and 1 HIGH level input voltage LOW level input voltage input bias current input capacitance logic 1 or logic 0 indicative, not tested 0.7VDD -0.3 -5 - -
Lock detect output signal; pin 20 open-drain output LOW level output voltage Isink = 0.4 mA 0.4 V
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Philips Semiconductors
Product specification
Low-voltage dual frequency synthesizer for radio telephones
SERIAL BUS TIMING CHARACTERISTICS VDD = VCC = 3 V; Tamb = 25 C unless otherwise specified. SYMBOL Serial programming clock; CLK tr tf Tcy tSTART tEND tW tSU;E tSU;DAT tHD;DAT Note input rise time input fall time clock period - - 100 10 10 - - - - - - - PARAMETER MIN. TYP.
UMA1020AM
MAX.
UNIT
40 40 - - - - - - -
ns ns ns
Enable programming; E delay to rising clock edge delay from last falling clock edge minimum inactive pulse width enable set-up time to next clock edge 40 -20 4000(1) 20 ns ns ns ns
Register serial input data; DATA input data to clock set-up time input data to clock hold time 20 20 ns ns
1. The minimum pulse width (tW) can be smaller than 4 s provided all the following conditions are satisfied: 512 a) Principal main divider input frequency f VCO > --------tW 32 b) Auxiliary main divider input frequency f AI > ----tW 3 c) Reference dividers input frequency f XTAL > ----tW
Fig.3 Serial bus timing diagram.
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Philips Semiconductors
Product specification
Low-voltage dual frequency synthesizer for radio telephones
APPLICATION INFORMATION
UMA1020AM
Fig.4 Typical application block diagram.
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Philips Semiconductors
Low-voltage dual frequency synthesizer for radio telephones
UMA1020AM
Product specification
Fig.5 Typical test and application diagram.
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Philips Semiconductors
Product specification
Low-voltage dual frequency synthesizer for radio telephones
PACKAGE OUTLINE SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm
UMA1020AM
SOT266-1
D
E
A X
c y HE vM A
Z
20
11
Q A2 pin 1 index A1 (A 3) Lp L A
1
e bp
10
detail X wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.20 0.13 D (1) 6.6 6.4 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 10 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT266-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 90-04-05 95-02-25
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Philips Semiconductors
Product specification
Low-voltage dual frequency synthesizer for radio telephones
SOLDERING SO or SSOP Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these cases reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SO and SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering SO Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. SSOP
UMA1020AM
Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). METHOD (SO OR SSOP) During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds at 270 to 320 C.
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Philips Semiconductors
Product specification
Low-voltage dual frequency synthesizer for radio telephones
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
UMA1020AM
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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Philips Semiconductors
Product specification
Low-voltage dual frequency synthesizer for radio telephones
NOTES
UMA1020AM
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Philips Semiconductors
Product specification
Low-voltage dual frequency synthesizer for radio telephones
NOTES
UMA1020AM
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Philips Semiconductors
Product specification
Low-voltage dual frequency synthesizer for radio telephones
NOTES
UMA1020AM
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Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970), Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. (852)2319 7888, Fax. (852)2319 7700 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (358)0-615 800, Fax. (358)0-61580 920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)7640 000, Fax. (01)7640 200 Italy: PHILIPS SEMICONDUCTORS S.r.l., Piazza IV Novembre 3, 20124 MILANO, Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5130, Fax. (03)3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)709-1412, Fax. (02)709-1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. (040)783749, Fax. (040)788399 (From 10-10-1995: Tel. (040)2783749, Fax. (040)2788399) New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546 Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430, Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 27 70, Fax. (0212)282 67 07 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (0181)730-5000, Fax. (0181)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 (from 10-10-1995: +31-40-2724825) SCD41 (c) Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
413061/1500/02/pp20 Document order number: Date of release: 1995 Jul 06 9397 750 00194

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